As a feature size of a control gate of flash memories decreases due to high integration of flash memories, a resistance of the control gate increases and thus problems, such as an RC delay and a voltage drop may occur. To address these problems, a metal layer is formed on a polysilicon layer and thermally treated to form a metal silicide layer. Thus, a control gate having a structure in which a metal silicide layer and a polysilicon layer are stacked has been introduced.
To obtain a resistance required for a control gate when a design rule is less than or equal to 50 nm, a thick metal silicide layer of 500Å or greater needs to be formed. However, as a silicidation reaction occurs for a narrow line width, voids are formed within the control gate or the profile of silicide deteriorates.